1. Field of the Invention
The present invention relates to a switching control circuit.
2. Description of the Related Art
In various electronic devices, there is used a voltage generating circuit generating an output voltage of a target level from an input voltage. Hereinafter, with reference to FIGS. 7 and 8, there will be given a description of a step-down voltage generating circuit 100, for example. The voltage generating circuit 100 is configured to include: a p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 101; a diode 102; an inductor 103; and a capacitor 104. A source electrode of the p-type MOSFET 101 is applied with an input voltage Vin. When the p-type MOSFET 101 is turned on, substantially the same voltage as the input voltage Vin is applied to the inductor 103. As a result, the capacitor 104 is charged, and thereby, an output voltage Vout is increased. Alternatively, when the p-type MOSFET 101 is turned off, a current passes through a loop configured with the diode 102, the inductor 103, and the capacitor 104 by energy accumulated in the inductor 103. As a result, the capacitor 104 is discharged, and thereby, the output voltage Vout is decreased. In this manner, the voltage generating circuit 100 is controlled so as to turn on and off the p-type MOSFET 101 with an appropriate timing so that the output voltage Vout can reach a target level.
In order to control switching of the p-type MOSFET 101, the voltage generating circuit 100 is configured to include a switching control circuit 105, and resistances 106 and 107, in addition to the above-described configuration. The switching control circuit 105 is configured to further include: an error amplifier circuit 111; a power supply 112; a comparison circuit 113; a triangular wave generator 114; a switching circuit 124; a p-type MOSFET 115; and an n-type MOSFET 116.
An input terminal of one polarity (+) (hereinafter, referred to as a + input terminal) of the error amplifier circuit 111 is applied with a reference voltage Vref1 according to the target level from the power supply 112, and an input terminal of the other polarity (−) (hereinafter, referred to as a − input terminal) thereof is applied with a feedback voltage Va obtained by dividing the output voltage Vout by a resistance ratio between the resistances 106 and 107. The error amplifier circuit 111 outputs an error voltage Vb (Vb in FIG. 8) obtained by amplifying an error between the reference voltage Vref1 and the feedback voltage Va. A + input terminal of the comparison circuit 113 is applied with the error voltage Vb and a − input terminal thereof is applied with a triangular-wave voltage Vt (Vt in FIG. 8) generated by the triangular wave generator 114, which changes at a predetermined frequency. The comparison circuit 113 outputs a voltage Vc of the H level during the period of time that the error voltage Vb is higher than the voltage Vt and outputs the voltage Vc of the L level during the period of time that the error voltage Vb is lower than the voltage Vt (Vc in FIG. 8). The H level indicates a voltage sufficient to turn on the n-type MOSFET 116 and sufficient to turn off the p-type MOSFET 115. The L level indicates a voltage sufficient to turn on the p-type MOSFET 115 and sufficient to turn off the n-type MOSFET 116. The switching circuit 124 is switched to a side of the comparison circuit 113 during the period of time that a comparison circuit 121 described later outputs the voltage Ve of the H level. Thus, based on the voltage Vc of the H level, the p-type MOSFET 115 is turned off, the n-type MOSFET 116 is turned on, and the p-type MOSFET 101 is turned on. As a result, the output voltage Vout is increased. On the other hand, based on the voltage Vc of the L level, the p-type MOSFET 115 is turned on, the n-type MOSFET 116 is turned off, and the p-type MOSFET 101 is turned off. As a result, the output voltage Vout is decreased. That is, as the error between the feedback voltage Va and the reference voltage Vref1 becomes greater, the error voltage Vb is increased, and the period during which the comparison circuit 113 outputs the voltage Vc of the H level becomes longer. As a result, the output voltage Vout is increased. As the error between the feedback voltage Va and the reference voltage Vref1 becomes smaller, the error voltage Vb is decreased and the period during which the comparison circuit 113 outputs the voltage Vc of the L level becomes longer. As a result, the output voltage Vout is decreased. In this manner, in the switching control circuit 105, the output voltage Vc of the comparison circuit 113 is so-called PWM (Phase Width Modulation)-controlled such that the feedback voltage Va matches the reference voltage Vref1.
There may be cases where the power supply line 109 is short-circuited due to adhesion, etc. of dust or solder to a power supply line 109 to which the output voltage Vout is applied, and as a result, the output voltage Vout is grounded, for example. In this case, the error between the reference voltage Vref1 and the feedback voltage Va becomes great, so that an on state of the p-type MOSFET 101 is continued. As a result, a current is continuously supplied to the p-type MOSFET 101, the inductor 103, and the capacitor 104. Consequently, the p-type MOSFET 101, etc., may be damaged. Therefore, the voltage generating circuit 100 is provided with a capacitor 108 in order to turn off the p-type MOSFET 101 when the power supply line 109 is short-circuited. The switching control circuit 105 is further provided with a comparison circuit 117, a power supply 118, an n-type MOSFET 119, a current source 120; the comparison circuit 121, a power supply 122, and a latch circuit 123.
A + input terminal of the comparison circuit 117 is applied with a reference voltage Vref2 (Vref2 in FIG. 8) and a − input terminal thereof is applied with the error voltage Vb. The reference voltage Vref2 is: lower than the error voltage Vb (between t105 and t106 in FIG. 8) in the case where the power supply line 109 is short-circuited; and higher than the error voltage Vb (linear error voltage Vb up to t101, for example) in the case where the output voltage Vout is at a target level. The error voltage Vb between t101 and t102 and between t103 and t104 shown in FIG. 8 indicates the error voltage Vb: in the case where a noise superimposition occurs on the power supply line 109, the resistances 106 and 107, etc., or on a connection line from a connection point between the resistances 106 and 107 to the − input terminal of the error amplifier circuit 111; or in the case where a short-circuited state of the power supply line 109 is released in a period shorter than a period T (between t105 and t106 in FIG. 8) elapsing before a charged voltage of the capacitor 108 reaches a reference voltage Vref3 (hereinafter, referred to as generation of noise, etc.). The comparison circuit 117 outputs the H level during the period of time that the error voltage Vb is lower than the reference voltage Vref2, and outputs the L level during the period of time that the error voltage Vb is higher than the reference voltage Vref2. The H level indicates a voltage sufficient to turn on the n-type MOSFET 119, and the L level indicates a voltage sufficient to turn off the n-type MOSFET 119. That is, the comparison circuit 117 outputs the L level during the period of time that the error voltage Vb is higher than the reference voltage Vref2 as a result of the short-circuit of the power supply line 109, the generation of noise, etc. When the n-type MOSFET 119 is turned off based on the L level, a current from the current source 120 is supplied to the capacitor 108, and thereby the capacitor 108 is charged. A + input terminal of the comparison circuit 121 is applied with the reference voltage Vref3 (Vref3 in FIG. 8) and a − input terminal thereof is applied with a voltage Vd (voltage Vd in FIG. 8) of the connection line 110. The connection line 110 is applied to the charged voltage of the capacitor 108. The reference voltage Vref3 is lower by a predetermined level than a charged voltage at the time that the capacitor 108 is fully charged, for example. The comparison circuit 121 outputs a voltage Ve of the H level during the period of time that the voltage Vd applied to the − input terminal is lower than the reference voltage Vref3, and outputs a voltage Ve of the L level during the period of time that the voltage Vd applied to the − input terminal is higher than the reference voltage Vref3 (Ve in FIG. 8). As the period of time between t101 and t102 or between t103 and t104 shown in FIG. 8, when the period of time during which the error voltage Vb is higher than the reference voltage Vref2 as a result of the generation of noise, etc. is shorter than the period T indicating the period until the charged voltage of the capacitor 108 reaches the reference voltage Vref3, the output of the comparison circuit 121 remains the voltage Ve of the H level. When the latch circuit 123 outputs the H level based on the voltage Ve of the H level, a switch state of the switching circuit 124 is held to the side of the comparison circuit 113. That is, even when the error voltage Vb is higher than the reference voltage Vref2 as a result of the generation of noise, etc., the p-type MOSFET 101 is controlled as to on and off based on the output voltage Vc of the comparison circuit 113. On the other hand, As the period of time between t105 and t106, when the period of time during which the error voltage Vb is higher than the reference voltage Vref2 as a result of the short-circuit of the power supply line 109 reaches the period T indicating the period until the charged voltage of the capacitor 108 reaches the reference voltage Vref3, the output of the comparison circuit 121 becomes the voltage Ve of the L level. When the latch circuit 123 latches the L level and outputs it based on the voltage Ve of the L level, the switching circuit 124 is switched to a side of the latch circuit 123. Thus, based on the L level via the switching circuit 124, the p-type MOSFET 115 is turned on and the n-type MOSFET 116 is turned off, so that the p-type MOSFET 101 is held in the off state. As a result, the supply of the current via the p-type MOSFET 101 to the inductor 103 and the capacitor 104 is interrupted, and thereby preventing the damage of the p-type MOSFET 101, etc. That is, if the state that the error voltage Vb is higher than the reference voltage Vref2 lasts for the period T elapsing before the charged voltage of the capacitor 108 reaches the reference voltage Vref3, the latch circuit 123 latches the L level, thereby holding the p-type MOSFET 101 in an off state (See Japanese Patent Laid-Open No. 2002-171749).
However, when there is generated noise making the voltage Vd as shown in t107 in FIG. 9 higher than the reference voltage Vref3 in the connection line 110 or the capacitor 108, the comparison circuit 121 outputs the voltage Ve of the L level, so that the p-type MOSFET 101 is held in the off state. That is, with respect to a temporary generation of noise, etc., in the power supply line 109, etc., the voltage generating circuit 100 prevents the p-type MOSFET 101 from being held in the off state by being provided with the capacitor 108, the comparison circuit 121, etc. However, with respect to a temporary generation of noise in the capacitor 108 or the connection line 110, measures to prevent the p-type MOSFET 101 from being held in the off state are not taken. As a result, when the voltage Vd higher than the reference voltage Vref3 is applied to the − input terminal of the comparison circuit 121, the p-type MOSFET 101 may be held in the off state even though the power supply line 109 is not short-circuited, and the output voltage Vout of a target level may not be able to be generated from the input voltage Vin.